计算机与通信工程学院 School of Computer and Communication Engineering
副教授
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蔡烁

发布时间: 2020-03-16 10:13:32 浏览量:

长沙理工大学计算机与通信工程学院研究生导师基本信息表


1、个人基本信息:


姓 名:蔡烁

性 别:男



出生年月:1982年10月

技术职称:副教授


毕业院校:湖南大学

学历(学位):博士


所在学科:信息与通信工程,计算机科学与技术

研究方向:容错计算、电路系统可靠性、集成电路设计与测试、物联网可靠性


2、教育背景:


2000.9-2004.6

浙江大学

信息工程,本科


2004.9-2007.6

湖南大学

信号与信息处理,硕士


2010.9-2015.4

湖南大学

计算机科学与技术,博士


3、目前研究领域:


1、电路系统可靠性

2、集成电路设计与测试

3、电路抗辐射加固设计

4、容错计算

5、复杂网络可靠性


4、已完成或已在承担的主要课题:


1、逻辑级破解纳米集成电路软错误可靠性评估难题的新方法,61702052,国家自然科学基金青年项目,2018.1-2020.12,主持,已完成

2、面向逻辑级超大规模集成电路软错误率分析方法研究,2020JJ4622,湖南省自然科学基金面上项目,2020.1-2022.12,主持,在研

3、空间辐射环境下纳米集成电路瞬态故障分析与可靠性评估,18A137,湖南省教育厅重点项目,2019.1-2021.12,主持,在研

4、大坝病害快速诊断与动态风险控制决策研究,湖南省水利科技项目,2020.1-2021.12,主持,在研

5、基于概率模型的数字电路可靠性评估方法研究,14C0028,湖南省教育厅一般项目,2014.9-2016.6,主持,已完成

6、基于SPPM并积运算的逻辑电路软错误可靠性评估,长沙理工大学基金项目,2018.1-2020.12,主持,已完成


5、已出版的主要著作:

王伟征,蔡烁,吴宏林,数字VLSI电路低费用低功耗测试技术,南方出版社,2018.12.30

6、已发表的学术论文:


[1]Shuo Cai, Binyong He, Weizheng Wang, et al. Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. Journal of Electronic Testing-Theory and Applications. 2020, 36(4): 469-483

[2]Shuo Cai, Binyong He, Sicheng Wu, et al. An Accurate and Efficient Approach for Estimating the Failure Probability of Logic Circuits, 2020 CCF Integrated Circuit Design and

Automation Conference, 2020: 1-15

[3]Shuo Cai, Weizheng Wang, Fei Yu, Binyong He. Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits. Journal of Electronic Testing - Theory and Applications. 2019, 35(2): 163-172

[4]Shuo Cai, Fei Yu, Yiqun Yang. Analysis of SET Pulses Propagation Probabilities in Sequential Circuits, 2017 the 4th International Conference on Advances in Electronics Engineering, 2017: 1-6

[5]Shuo Cai, Yinbo Zhou, Peng Liu, Fei Yu, Wei Wang. A Novel Test Data Compression Approach Based on Bit Reversion. IEICE Electronics Express. 2017, 14(13): 1-11

[6]Shuo Cai, Fei Yu, Weizheng Wang, Tieqiao Liu, Peng Liu, Wei Wang. Reliability Evaluation of Logic Circuits Based on Transient Faults Propagation Metrics. IEICE Electronics Express. 2017, 14(7): 1-7

[7]Cai Shuo, Kuang Jishun, Liu Tieqiao, Wang Weizheng. Soft Error Susceptibility Analysis for Sequential Circuit Elements Based on EPPMs. Journal of Semiconductor Technology and Science. 2015, 15(2): 168-176

[8]蔡烁,邝继顺,张亮,刘铁桥,王伟征.基于差错传播概率矩阵的时序电路软错误可靠性评估.计算机学报. 2015, 38(5): 923-931

[9]蔡烁,邝继顺,刘铁桥,凌纯清,尤志强.基于伯努利分布的逻辑电路可靠度计算方法.电子学报. 2015, 43(11):2292-2297

[10]蔡烁,邝继顺,刘铁桥,王伟征.考虑信号相关性的逻辑电路可靠度计算方法.电子学报.2014, 42(8): 1660-1664

[11]蔡烁,邝继顺,刘铁桥,周颖波.一种高效的门级电路可靠度估算方法.电子与信息学报. 2013, 35(5): 1262-1266

[12]蔡烁,胡航滔,王威.基于深度卷积网络的高分遥感图像语义分割.信号处理, 2019. 35(12): 2010-2016

[13]Shuo Cai, Fei Yu, Yiqun Yang. Analysis of SET pulses propagation probabilities in sequential circuits. 2nd International Conference on Reliability Engineering (ICRE), 2017.12.20-2017.12.22

[14]Weizheng Wang, Zhuo Deng, Jin Wang, Arun Kumar Sangaiah,Shuo Cai, Zafer Almakhadmeh, Amr Tolba.Securing Cryptographic Chips Against Scan-Based Attacks in Wireless Sensor Network Applications. Sensors. 2019, 19: 1-17

[15]Weizheng Wang, Jincheng Wang, Wei Wang, Peng Liu,Shuo Cai, A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks, IEEE Access, 2019, 7: 22206-22213

[16]Yu Fei, Zhang Zinan, Liu Li, Shen Hui, Huang Yuanyuan, Shi Changqiong,Cai Shuo, Song Yun, Du Sichun, Xu Quan, Secure communication scheme based on a new 5D multistable four-wing memristive hyperchaotic system with disturbance inputs, Complexity, 2020, 2020: 5859273

[17]Fei Yu, Lixiang Li, Lei Gao,Shuo Cai, Yun Song. A Colpitts Quadrature VCO for 2.4GHz Bluetooth/WLAN Applications. Solid State Technology. 2019, 62(1): 25-29

[18]Fei Yu, Lei Gao, Li Liu, Shuai Qian,Shuo Cai, Yun Song. A 1 V, 0.53 ns, 59μW Current Comparator Using Standard 0.18μm CMOS Technology. Wireless Personal Communications. Published online: 18 October 2019

[19]Yu Fei, Liu Li, Xiao Lin, Li Kenli,Cai Shuo, A robust and fixed-time zeroing neural network for computing time-variant nonlinear equation using a novel nonlinear activation function, Neurocomputing, 2019, 350: 108-116

[20]Peng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang,Shuo Cai. Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. IEEE Asian Test Symposium. 2018: 25-29

[21]Peng Liu, Zhiqiang You, Jishun Kuang, Michael Elimu,Shuo Cai, Weizheng Wang. Logic Operation-based Design for Testability Method and Parallel Test Algorithm for 1T1R Crossbar. Electronics Letters. 2017, 53(25): 1631-1632

[22]Wang Weizheng, Wang JinCheng,Cai Shuo, Su Wei, and Xiang Lingyun. Compression-Friendly Low Power Test Application Based on Scan Slices Reusing. Journal of Semiconductor Technology and Science. 2016, 16(4): 463-469

[23]Liao Wu, Jishun Kuang, Zhiqiang You, Peng Liu,Shuo Cai. A Parallel-SSHI Rectifier for Ultra-Low-Voltage Piezoelectric Vibration Energy Harvesting. IEICE Electronics Express.2016, 13(17): 1-8

[24]Liu Tieqiao, Zhou Yingbo, Liu Yi,Cai Shuo.Harzard-Based ATPG for Improving Delay Test Quality. Journal of Electronic Testing-Theory and Applications. 2015, 31(1): 27-34

[25]Liu Tieqiao, Kuang Jishun,Cai Shuo, You Zhiqiang. An Efficient Small-Delay Faults Simulator Based on Critical Path Tracing. International Journal of Circuit Theory and Applications. 2015, 43(8): 1015-1023

[26]Weizheng Wang,Cai Shuo, Lingyun Xiang. SOC Test Compression Scheme Sharing Free Variables in Embedded Deterministic Test Environment. Journal of Semiconductor Technology and Science. 2015, 15(3): 397-403

[27]Weizheng Wang,Shuo Cai, Lingyun Xiang. Scan Power-Aware Deterministic Test Scheme Using a Low-Transition Linear Decompressor. International Journal of Electronics.2015, 102(4): 651-667

[28]邝继顺,周颖波,蔡烁,皮宵林.一种用于测试数据压缩的改进型EFDR编码方法.电子测量与仪器学报. 2015, 29(10): 1464-1471

[29]Wang Weizheng,Cai Shuo, Xiang Lingyun. Reducing Test Power and Improving Test Effectiveness for Logic BIST. Journal of Semiconductor Technology and Science. 2014, 14(5): 640-648

[30]刘铁桥,邝继顺,蔡烁,尤志强.一种将测试集嵌入到Test-Per-Clock位流中的方法.计算机研究与发展. 2014, 51(9): 2022-2029

[31]Liu Tieqiao, Kuang Jishun,Cai Shuo, You Zhiqiang. An Effective Logic BIST Scheme Based on LFSR-Reseeding and TVAC. International Journal of Electronics. 2014, 01(9): 1217-1229

[32]Tieqiao Liu, Jishun Kuang, Zhiqiang You,Shuo Cai. An Effective Deterministic Test Generation for Test-Per-Clock Testing. IEEE Aerospace and Electronic Systems Magazine. 2014, 29(5): 25-33

[33]凌纯清,邝继顺,尤志强,谢鲲,蔡烁.基于奇偶保持的低成本高速量子逻辑电路在线检错方法.第八届中国测试学术会议CTC2014. 2014.中国武汉: 357-366


7、所获学术荣誉及学术影响:

1、湖南省青年骨干教师培养对象

2、中国计算机学会会员

3、中国通信学会会员

4、湖南省计算机学会理事

5、湖南省人工智能学会会员


E-mail: caishuo@csust.edu.cn








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